1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a layout of a semiconductor memory device having a hierarchical input/output (I/O) line pair structure.
2. Description of the Background Art
In semiconductor memory devices, chip areas have been increased to ensure larger capacity. However, when the chip area increases to ensure larger capacity, signal lines are extended longer, resulting in signal propagation delay, causing delay in access time, degrading electrical property, and causing increased operational current and standby current.
Generally, in order to suppress operational current, a memory block included in the semiconductor memory device is divided, and divided blocks are operated separately. However, if the number of division increases the chip area also increases, and therefore, this approach has its limit. Meanwhile, as the device comes to be miniaturized, difficulty in processing comes to be more severe. Micro short-circuit in a memory cell caused by unsuccessful processing has become a cause increasing the standby current.